In general, every operational amplifier having an input differential pair of transistors has an offset voltage associated therewith due in part to an uncontrollable mismatch of the transistors. When different voltage potentials are applied to the input electrodes of the differential pair of transistors, the associated offset voltage drifts as a function of the magnitude of the differential input voltage. When an operational amplifier is coupled in a unity gain configuration, offset voltage drift may be substantial because offset drift increases exponentially as a function of the differential input. Others have used clamping diodes across the control electrodes of the differential pair of transistors to limit the potential difference. However, the use of clamping diodes couples one input signal source to the other via a low impedance path and defeats the advantage of high input impedance of MOS differential amplifiers. Others have clamped the control electrodes of the differential pair of transistors by using additional transistors without substantially loading the external circuitry as taught in U.S. Pat. No. 4,206,418 by Dingwall. Such circuits however slow the response time of the differential amplifier by using both gating and clamping transistors to limit the input differential voltage.